CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pick-up such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.
Current CMOS image sensors comprise an array of CMOS Active Pixel Sensor (APS) cells, which are used to collect light energy and convert it into readable electrical signals. Each APS cell comprises a photosensitive element, such as a photodiode, photogate, or photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in an underlying portion thereof. A read-out circuit is connected to each pixel cell and often includes a diffusion region for receiving charge from the photosensitive element, when read-out. Typically, this is accomplished by a transistor device having a gate electrically connected to the floating diffusion region. The imager may also include a transistor, having a transfer gate, for transferring charge from the photosensitive element to the floating diffusion region, and a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transfer.
As shown in FIG. 1, a typical CMOS APS cell 10 includes a pinned photodiode 20 having a pinning layer 18 doped p-type and, an underlying lightly doped n-type region 17. Typically, the pinned diode 20 is formed on top of a p-type substrate 15 or a p-type epitaxial layer or p-well surface layer having a lower p-type concentration than the diode pinning layer 18. The n− region 17 and p region 18 of the photodiode 20 are typically spaced between an isolation region (not shown) and a charge transfer transistor gate 25 which are surrounded by thin spacer structures 23a,b. The photodiode 20 thus has two p-type regions 18 and 15 having a same potential so that the n− region 17 is fully depleted at a pinning voltage (Vp). The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value, Vp, when the photodiode is fully depleted. In operation, light coming from the pixel is focused down onto the photodiode through the diode where electrons collect at the n-type region 17. When the transfer gate 25 is operated, i.e., turned on, the photo-generated charge is transferred from the charge accumulating doped n− type region 17 via a transfer device surface channel 16 to a floating diffusion region 30 which is doped n+ type.
In conventional processes for fabricating the pinning layer 18 over the photodiode in the prior art APS cell 10 shown in FIG. 1, it is the case that some amount of p-type doping 29 overlaps onto the transfer gate 25 which is normally formed of intrinsic polysilicon or low level p-type doped 27. This is a result of mask overlay tolerance or displacement of the mask edge during fabrication. Subsequently, during formation of the n+ type doped floating diffusion region 30, the gate is processed to include a low level n− type doped region 28. The presence of this p doping has an effect of reducing the efficiency and dynamic range of the gate, particularly by causing variations in transfer gate voltage thresholds (Vt). This will cause the transfer gate to not turn on completely. Also, because of lithographic alignment issues, the position of the p ‘overlap’ onto the gate varies, leading to performance variability.
It would thus be highly desirable to provide a CMOS image sensor APS cell and method of manufacture that avoids these limitations.